1. Field of the Invention
The present invention relates to a duplication processor of a switching system, and more particularly to an apparatus and a method for verifying memory coherency of a duplication processor.
2. Description of the Background Art
Generally, a processor of a switching system has a duplication structure of two processors, having the same construction to each other, that is, an active processor which is operated in an active mode and a standby processor which is operated in a standby mode
FIG. 1 is a schematic block diagram of-a duplication processor including an active processor 10 and a standby processor 20.
As shown in the drawing, the active processor 10 includes a first CPU 11, a first memory controller 12, a local bus controller 13 and a first duplication pathway 14.
The first CPU 11 performs a general controlling operation of the processor, and for verifying memory coherency, it starts a standby memory read transaction (SMRT) and informs the local bus controller 13 of it.
The first memory controller 12 arbitrates a processor bus (P-bus) according to a transaction request by the local bus controller 13.
The local bus controller 13 requests the bus arbitration (BA) from the first memory controller 12 according to the transaction of the CPU 11, and at the same time, outputs a standby memory read address outputted from the CPU 11 to the first duplication pathway 14.
The first duplication pathway 14 provides a path for the read address of the standby memory 23 and the data read from the standby memory 23, and discriminates clock rates of the processor bus (P-bus), a duplication bus (D-bus) and a duplication channel (D-ch).
Having a structure symmetrical to that of the active processor 10, the standby processor 20 includes a second memory controller 22, a standby memory 23, a processor bus controller 24 and a second duplication pathway 25.
The second memory controller 22 arbitrates bus use of the processor bus controller 24 and reads the standby memory 23 according to a request of memory reading by the processor bus controller 24.
The second duplication pathway 25 performs the same operation as that of the first duplication pathway 14.
The operation of the duplication processor constructed as described will now be described.
When the first CPU 11 starts a standby memory read transaction (SMRT), the local bus controller 13 requests a bus arbitration (BA) from the first memory controller 12. When a bus use right is given from the first memory controller 12, the local bus controller 13 outputs a read address (RA) of the standby memory 23 outputted from the first CPU 11 to the first duplication pathway 14. Then, the first duplication pathway 14 transmits the inputted address (RA) through the duplication channel (D-ch) to the standby processor 20.
Thereafter, when the address (RA) is inputted through the second duplication pathway 25 from the active processor 10, the processor bus controller 24 requests bus arbitration from the second memory controller 22. And, when the bus use is allowed by the second memory controller 22, the processor bus controller 24 outputs the read address (RA) to the second memory controller 22.
Consequently, the second memory controller 22 reads a data corresponding to the read address (RA) from the standby memory 23 under the control of the processor bus controller 24 and outputs the data to the processor bus controller 24, and then, the processor bus controller 24 transmits the read data of the standby memory 23 through the second duplication pathway 25 to the active processor 10.
Accordingly, the local bus controller 13 transmits the read data of the standby memory 23 which has been received from the standby processor 20 through the first duplication pathway 14, to the CPU 11, thereby completing transaction.
Thereafter, the CPU 11 repeatedly performs the above described transaction operation to read all the data from the standby memory 23, and compares the data with a data stored in an active memory (not shown) to perform a coherency verifying operation of the memory.
In this manner, the conventional duplication processor has an advantage in that the clock rates of the processor bus (P-bus), the duplication bus (D-bus) and the duplication channel (D-ch) can be discriminated by virtue of the duplication pathway existing in both processors.
However, the conventional duplication processor structure employs a hand-shake method to perform the transaction operation. Thus, even though the active processor starts reading operation of the standby memory, a long time is taken for transaction according to an operation state of the D-ch and the standby processor. As a result, the CPU of the active processor should wait to proceed to other operation until the transaction operation is completely performed.
In addition, in the conventional duplication processor structure, each transaction is performed by a single beat, resulting in that a long time is to be taken to perform coherency verifying for all the standby memories,